FIG. 1 (prior art) shows an example of a conventional memory system 100. In this example, memory system 100 resides on a computer motherboard 105 and is actually a subsystem of the motherboard. System 100 includes a plurality of female electrical connectors 110, each of which accepts a memory module 115 (only one of which is shown here). Each memory module 115 contains a plurality of memory devices 120, typically packaged as discrete integrated circuits (ICs). Memory devices 120 are usually some type of read/write memory, such as Dynamic Random Access Memories (DRAMS), Static Random Access Memories (SDRAMs), Flash RAM, or other types. Read-Only Memories (ROM) devices might also be used.
Motherboard 105 includes a memory controller 125 connected via conductive traces 130 to connectors 110. Memory controller 125 communicates with memory modules 115 through conductive traces 130. Memory controller 125 also has an interface (not shown) that communicates with other components on the motherboard, allowing those components to read from and write to memory.
Each memory module 115 typically contains a fixed-width data path interface. The fixed-width nature of the interface is generally a result of a desire to create an industry standard interface that can accommodate interoperable modules from a large number of suppliers.
System 100 works with different numbers of memory modules 115 installed, and with modules having different memory capacities and/or organizations. However, a system such as this is normally designed for a specific system data path width, i.e., for a specified number of data bit lines from controller 125 to memory modules 115.
Memory devices can be targeted to a wide variety of markets with very different sets of cost and performance constraints; consequently, the optimal device width can vary significantly from one application to the next. Unfortunately, these variations make it difficult for memory suppliers and distributors to accurately predict the customer demand mix for memory devices of various widths. Inaccuracies in demand-mix prediction can cause supply/demand imbalances and inventory management difficulties, which in turn can lead to pricing instability and highly variable profit margins. Furthermore, a memory device manufacturer may find that optimizing the cost for each target device width means a different design at the die level and potentially at the package level. This can increase the time-to-market and level of financial and engineering resources required to deliver each of these products to market.
Fixed-width devices have other drawbacks related to inflexible data path configuration. Because the system memory interface width and memory device interface widths are fixed, the addition of more memory devices or modules to the system typically requires multiple ranks, which generally necessitates the use of a multi-drop datapath topology. Adding more drops to the system tends to degrade signaling performance.
One way to reduce time-to-market and resource requirements is to create a common die design and package pinout that can support a variety of device data path widths. Some memory manufacturers support this capability through memory designs that allow configurations to be postponed until relatively late in the manufacturing process. A configuration is typically selected through one of several possible schemes, such as fuse or anti-fuse programmability, wire-bonding options, or upper level metal mask changes. This flexibility allows the device to be tested at the target width and sold as a fixed-width device.
Another way to reduce time-to-market and resource requirements associated with fixed-width memories is to use a memory design in which the width (e.g., the number of data pins) can be dynamically changed to suit the needs of a particular system. One such memory design is depicted in U.S. patent application Ser. No. 5,893,927 to William P. Hovis, which is incorporated herein by reference. FIG. 2, taken from the Hovis patent, illustrates a conventional synchronous dynamic random access memory (SDRAM) 200 having a programmable device width. SDRAM 200 includes a clock generator 205 that provides clock signals to various components of SDRAM 200. A command decoder 210 receives chip select /CS, row enable /RAS, column enable /CAS and write command /W inputs. (The “/” preceding the signal names identifies the signals as active low. Overbars are used in the figures for the same purpose.) Command decoder 210 recognizes, for example, a write command when /CS, /CAS, and /W are simultaneously asserted (i.e., logic low). Command decoder 210 then outputs the command to some control logic 215, which controls the operation of the other components of SDRAM 200 based on the received command.
Besides the commands of /CS, /RAS, /CAS and /W, command decoder 210 also recognizes commands based on a combination of /CS, /RAS, /CAS, and /W. For instance, command decoder 210 decodes the simultaneous receipt of /CS, /RAS, /CAS, and /W as a mode register set command. When a mode register set command is received, control logic 215 causes a mode register 220 to latch the address data on address inputs A0-A10 and BA0-BA1.
The data on address inputs A0-A10, generally, represent either a row or column address, whereas the data on address inputs BA0-BA1, generally, represent a bank address. The bank address inputs BA0-BA1 specify one of the memory banks A-D discussed in detail below. During the mode register set operation, however, the data on address inputs A0-A10 and BA0-BA1 represent commands. Hereinafter, the address inputs and the data thereon will generically be referred to as address inputs.
SDRAM 200 includes a row address buffer and refresh counter 225 and a column address buffer and burst counter 230, both of which connect to address inputs A0-A10 and BA0-BA1. The row address buffer portion latches the address inputs at row-access-strobe (RAS) time and provides the row address to the appropriate row decoder 235. The refresh counter portion refreshes the memory. The column address buffer portion latches the address inputs at column-access-strobe (CAS) time and provides the column address to the appropriate column decoder 240. The burst counter portion controls the reading/writing of more than one column based on a pre-set burst length.
The memory of SDRAM 200 is divided into four memory banks A-D that can be independently and simultaneously selected. Each memory bank A-D has associated therewith a row decoder 235, a sense amplifier 255, and a column decoder 240. Based on the address latched by the row address buffer and refresh counter 225, one of row decoders 235 enables a row of bits in the corresponding bank. An associated sense amplifier 255 latches the columns of this row via sense amplification, and the associated column decoder 240 outputs one or more bits depending on the device width and burst length. Sense amplifier 255 typically represents a combination of column I/O amplifiers arranged along an edge of the array of banks and lower-level sense amplifiers interleaved between memory cells.
SDRAM 200 includes configuration logic 260 for setting the device width. Configuration logic 260 connects to mode register 220, and from there receives a memory-width configuration value stored in register 220 during device configuration. Based on this information, configuration logic 260 configures a data control circuit 265, a latch circuit 270, and an input/output (I/O) buffer 275 to obtain the device width associated with the memory-width configuration value. Specifically, configuration logic 260 controls switches and multiplexers in data control circuit 265 such that the number of active I/O drivers corresponds to the programmed device width.
Data control circuit 265 is connected to each column decoder 240, and to data I/O pin(s) DQ(s) via latch circuit 270 and input/output buffer 275. During a read operation, sense amplifiers 255 and column decoders 240 output data to data control circuit 265 based on the row enabled by decoder 235, the column enabled by decoder 240, and the burst length. Data control circuit 265 then routes the data to the number of I/O drivers set based on the device width. The data from the I/O drivers is then latched by the latch circuit 270, buffered by I/O buffer 275, and output on the data I/O pin(s) DQ(s). The number of I/O pin(s) DQ(s) corresponds to the device width.
During a write operation, SDRAM 200 receives data over the I/O pin(s) DQ(s). This data is buffered by I/O buffer 275, latched by latch circuit 270, and received by data control circuit 265. Data control circuit 265 sends the data to the appropriate column decoders 240 for storage in the memory banks A-D according to the enabled row and column.
SDRAM 200 also includes an input DQM to latch circuit 270 for every 8 bits of input/output. For instance a x16 SDRAM will have two inputs DQM0 and DQM1. When enabled, the input DQM prevents reading or writing the remainder of a burst. In this manner, the burst length can be controlled.
Each read operation presents an entire row of data to sense amps 255. Each write operation similarly involves an entire row. In SDRAM 200, changing the memory width merely changes the number of bits selected from the accessed row: the narrower the memory configuration, the fewer bits are selected from the accessed row. Since the power required to perform a row access does not change with changes in device width, the relative power efficiency of row accesses reduces with memory width.